Integrated circuits are manufactured by forming multiple layers of semiconductor materials generally with repeated and fixed patterns to develop a plurality of "dice" on a thin plane or substrate, i.e., a semiconductor wafer. The wafers are then cut into individual die for further processing and packaging. The dice must be inspected and tested to insure the quality and reliability of the final products made from the semiconductor dice. Sometimes dice are tested after they are cut into individual die from the whole wafer. However, dice may also be tested simultaneously, in groups consisting of part of a wafer or a whole wafer. Testing dice before separation is often more effective.
The testing operation is typically performed at a wafer level before the wafers are sawed apart into individual die. The testing system typically comprises a test controller, which executes and controls the test programs; a wafer dispensing system, which mechanically handles and positions the wafers for testing; a probe card, which maintains an accurate mechanical contact with the device under test (DUT) and provides an electrical interface between the test controller and the DUT. The probe card includes a printed circuit board known as the "performance board." A performance board may be designed for individualized devices or IC families. The probe card also has a plurality of test probes which are accurately positioned to coincide with the input/output (I/O) pads of the DUT.
Under control of the test controller, a set of testing signals including specific combinations of voltages and currents are generated and transmitted to the DUT via the performance board and the test probes. The output of the dice in response to the test signals are detected and transmitted by the probes to the test controller via the performance board. The voltage, current or frequency responses from the DUT are analyzed and compared with a set of predetermined allowable ranges. Dice which fail to meet the testing criteria are identified and rejected and the remainder of the test chips are accepted for further process.
A conventional type of wafer probe card consists of a set of fine styluses or probes mounted on the performance board. The probes are arranged so that their tips form a pattern identical to that of the DUT's contact pads. The other ends of the probes are soldered to the traces of the printed circuits on the performance board for further connection to the test controller. The wafer dispensing system brings the wafer to be tested to an aligned position under the probe card and raises the wafer until proper contacts are established between the probes and DUT's I/O pads.
Membrane probe technology has been developed by forming an array of microcontacts, generally known as contact bumps, on a thin and flexible dielectric film, i.e., a membrane. For each contact bump, a transmission line is formed on the membrane for electric connection to the performance board. The contact bumps are often formed by metal plating methods. The transmission lines are formed by use of photolithographic methods. Contact bumps are formed directly on the membrane, and become an integral part of the membrane probe, unlike conventional probes which require mechanical attachment of electrical contacts such as needles or blades. Contact bumps can be formed to create a large number of contacts with high probe density. Additionally, improvements in mechanical and electrical performance are realized by membrane probes because of the simplicity of configuration.
One critical prerequisite for successful I/C test by either the membrane or conventional probe cards is to establish proper electrical contact between the probes and the DUT's I/O pads. In practical testing operations, the probe card and its probe tips or the contact bumps may not be exactly coplanar with the surface of the DUT's I/O pads. Furthermore, the electrical contacts on the membrane, and the pads or other types of contacts on the semiconductor die may be somewhat fragile. It is important, therefore, that an accurate and controllable force be employed when contacting probes or membrane contacts to die contacts.
Consequently, a semiconductor wafer contact system is desirable which provides force focused only in areas desired to be contacted on the semiconductor die, thereby giving increased confidence that all desired contacts are successfully made without creating excessive force on any individual contact. Furthermore, a system is desirable which is capable of dealing with local surface irregularities and nonplanarities due to process variations, etc., of wafer pad or bump heights, or fixture contact height. Furthermore, a system is desirable which allows device testing on a group of die or at a wafer level, rather than just at an individual die level.